1. Field of the Invention
The present invention relates to an Input/Output (I/O) circuit for a CMOS multiple-power-supply integrated circuit, and more particularly to a semiconductor I/O circuit for protecting the integrated circuit. The semiconductor I/O circuit is designed to minimize the circuit scale of the semiconductor circuit as well as to reduce the effects of noise that an analog circuit receives from a digital circuit.
2. Description of the Related Art
In digital semiconductor integrated circuits, protection circuits are typically not provided in the power supply or ground terminals since a general protection circuit is normally arranged between each I/O terminal and an internal circuit corresponding to the power supply and ground. However, in an integrated circuit that operates with plural power supply units (e.g., analog and digital power supply units for supplying power to analog and digital circuitry, respectively), protection circuits are also needed between the I/O terminals (e.g., analog I/O terminals) of one block or group of cells and a power supply or ground (e.g., digital power or ground) of another block or group of cells.
An example of a conventional semiconductor integrated circuit having both analog and digital circuitry (e.g., an analog/digital mixed semiconductor integrated circuit) is shown in FIGS. 3A and 3B. In the I/O circuit shown in FIG. 3A, in order to prevent noise generated by the digital circuitry from interfering with the analog circuitry, the I/O terminals that are connected to power supply lines 16, 18, 20 and GND lines 17, 19, 21 are separated. More specifically, as shown in FIG. 3A, analog power supply line 16, and analog GND line 17 run along and are typically input via a pair of terminals provided along analog I/O terminals 11. Pads 51 are provided in each of the terminals. Digital power supply lines 18 and 20 and digital GND lines 19 and 21 run along and are input via one or more terminals provided along digital I/O terminals 14 and 15, respectively. As shown in FIG. 3A, gaps 25 and 26 are provided between the analog and digital terminals to separate the analog and digital terminals from each other. As shown even more clearly in the layout view depicted in FIG. 3B, typically the analog power terminal and analog ground terminal are arranged between the analog I/O terminals as shown. Gaps 25 and 26 are provided between the analog I/O terminals and the digital I/O terminals 14 and 15, as shown, for isolating the analog and digital terminals from each other.
However, in the I/O circuit shown in FIG. 3, protection circuitry is not provided between the analog circuitry (e.g. power supplied to the analog circuitry) and the digital circuitry (e.g., power supplied to the digital circuitry). Therefore, an Electrostatic Discharge (ESD) event or a "latch up" is likely to occur when an over current or over voltage occurs on an analog I/O terminal. In addition, gaps 25 and 26, necessary for isolating the analog and digital I/O terminals, occupy valuable space on the integrated circuit.
To overcome such problems, attempts have been made at providing circuitry for protecting from ESD events. An example of conventional I/O circuitry used in an analog/digital mixed semiconductor integrated circuit for protecting from ESD events is shown in FIG. 4. In the I/O circuit shown in FIG. 4, resistors 28 and 29 are provided in gaps 25 and 26, respectively. Resistors 28 and 29 connect the analog GND line 17 with the digital GND lines 19 and 21, respectively. The resistors function as protection circuits for preventing the semiconductor integrated circuit from being damaged by an Electrostatic Discharge (ESD) event.
However, although in the circuit shown in FIG. 4 the digital GND lines and the analog GND line are connected with each other via resistors, even in this I/O circuit, damage from an ESD event or a "latch up" is not sufficiently prevented. That is, since there is no protection circuitry provided between the analog circuitry and the digital power supply line or between the digital circuitry and the analog power supply line an ESD event or a "latch up" may still damage the integrated circuitry. Moreover, since the resistors are provided in gaps 25 and 26, an increased area is still required on the semiconductor chip for the I/O circuitry.
Another example of conventional I/O circuitry used in an analog/digital mixed semiconductor integrated circuit is shown in FIGS. 5A and 5B. As shown in FIG. 5A, protection circuits 30 and 31 are provided in gaps 25 and 26, respectively. Protection circuits 30 and 31 are shown more clearly in FIGS. 7B and 7A, respectively.
Protection circuit 31 connects analog power supply line 16 and analog GND line 17 with digital power supply line 20 and digital GND line 21, as shown. Protection circuit 30 connects analog power supply line 16 and analog GND line 17 with digital power supply line 18 and digital GND line 19, as shown. Protection circuits 30 and 31 consist of N-channel MOS transistors 30a, 30b and N-channel MOS transistors 31a, 31b, respectively, as shown. As shown in FIG. 5B, protection circuits 30 and 31 are provided in addition to protection circuits 50a which are typically provided for each I/O terminal.
Using the protection circuitry shown in FIGS. 5 and 7, the power supply can be protected from an over current or over voltage by the use of the protection circuits provided in the I/O circuit. That is, in the I/O circuit shown in FIG. 5, electric current does not flow through the protection circuits even when there is a potential difference between the analog and digital power supply lines.
However, this type of I/O circuit, because of the arrangement of the analog and digital I/O terminals, requires an increased area for the I/O circuitry on the semiconductor substrate since transistors have to be provided between the analog power supply line and the digital power supply lines as well as between the analog GND line and the digital GND lines. That is, as shown clearly in FIG 5B, because of the typical arrangement of the cells, protection circuits are not provided in the analog power cell and the analog ground cell, thus resulting in unused and wasted areas on the semiconductor circuit.
Another example of conventional I/O circuitry is disclosed in Japanese Laid-Open Patent No. 106455/95. Such I/O circuitry is used in an analog/digital mixed semiconductor integrated circuit and is described by reference to FIG. 6. The I/O circuit shown in FIG. 6 is used in a semiconductor integrated circuit driven by three power supply lines 32-34, and is equipped with a protection circuit 36 for preventing the semiconductor integrated circuit from being damaged by an Electrostatic Discharge (ESD) event. The protection circuit 36 consists of N-channel MOS transistors 36a, 36b, 36d connecting power supply lines 32-34, respectively, with a GND line 35, and N-channel MOS transistors 36c, 36e, 36f connecting power supply lines 32-34, with each other.
However, the I/O circuit shown in FIG. 6 requires that a plurality of power supply lines run through the I/O circuit, restricting the effective use of the area of the I/O circuit.